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| (R) HI-390 Data Sheet August 2002 FN4754.1 Dual SPDT CMOS Analog Switch The Hl-390 switch is a monolithic device fabricated using CMOS technology and the Intersil dielectric isolation process. This device is TTL compatible and features low leakage and supply currents, low and nearly constant ON resistance over the analog signal range, break-before-make switching and low power dissipation. Features * Analog Signal Range (15V Supplies) . . . . . . . . . . . 15V * Low Leakage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40pA * Low On Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 35 * Break-Before-Make Delay . . . . . . . . . . . . . . . . . . . . 60ns * Charge Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30pC Ordering Information PART NUMBER HI1-0390-2 TEMP. RANGE (oC) -55 to 125 PACKAGE 16 Ld CERDIP PKG. NO. F16.3 * TTL Compatible * Symmetrical Switch Elements * Low Operating Power. . . . . . . . . . . . . . . . . . . . . . . 1.0mW Pinout Switch States shown for a Logic "1" Input HI-390 (CERDIP) TOP VIEW D1 1 NC 2 D3 3 S3 4 S4 5 D4 6 NC 7 D2 8 16 S1 15 IN 1 14 V13 GND 12 NC 11 V+ 10 IN 2 9 S2 Applications * Sample and Hold (i.e., Low Leakage Switching) * Op Amp Gain Switching (i.e., Low On Resistance) * Portable, Battery Operated Circuits * Low Level Switching Circuits * Dual or Single Supply Systems Functional Diagram S IN N P D LOGIC 0 1 SW1, SW2 OFF ON SW3, SW4 ON OFF 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002. All Rights Reserved HI-390 Schematic Diagrams SWITCH CELL A V+ MN1B MN2B MP5B MP4B IN MN3B OUT MN4B MN5B MP3B MP2B MP1B A V- DIGITAL INPUT BUFFER AND LEVEL SHIFTER V+ D2A 200 LOGIC IN D1A GND VSWITCH CELL DRIVER (ONE PER SWITCH CELL) MN1A MN2A MN3A MN4A MN5A MN6A MN7A MN8A A A MP1A MP2A MP3A MP4A MP5A MP6A MP7A MP8A 2 HI-390 Absolute Maximum Ratings Voltage Between Supplies (V+ to V-) . . . . . . . . . . . . . . . . . . . . 44V Digital Input Voltage. . . . . . . . . . . . . . . . . . . . . . (V+) +4V to (V-) -4V Analog Input Voltage . . . . . . . . . . . . . . . . . . (V+) +1.5V to (V-) -1.5V Thermal Information Thermal Resistance (Typical, Note 1) JA ( oC/W) JC (oC/W) CERDIP Package. . . . . . . . . . . . . . . . . 75 20 Maximum Junction Temperature Hermetic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC Operating Conditions Temperature Ranges HI-390-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications Supplies = +15V, -15V; VIN = Logic Input. VIN for Logic "1" = 4V, for Logic "0" = 0.8V, Unless Otherwise Specified TEST CONDITIONS TEMP (oC) MIN TYP MAX UNITS PARAMETER DYNAMIC CHARACTERISTICS Switch ON Time, tON Switch OFF Time, tOFF Break-Before-Make Delay, tOPEN Charge Injection Voltage, V OFF Isolation Input Switch Capacitance, C S(OFF) Output Switch Capacitance, CD(OFF) Output Switch Capacitance, CD(ON) Digital Input Capacitance, CIN DIGITAL INPUT CHARACTERISTICS Input Low Level, VINL Input High Level, V INH Input Leakage Current (Low), IINL Input Leakage Current (High), IINH ANALOG SWITCH CHARACTERISTICS Analog Signal Range ON Resistance, r ON 25 25 25 (Note 7) (Note 6) 25 25 25 25 25 25 - 210 160 60 3 60 16 14 35 5 300 250 - ns ns ns mV dB pF pF pF pF Full Full (Note 5) (Note 5) Full Full 4 - - 0.8 1 1 V V A A Full (Note 2) 25 Full -15 - 35 40 0.04 1 0.04 1 0.03 0.5 +15 50 75 1 100 1 100 1 100 V nA nA nA nA nA nA OFF Input Leakage Current, IS(OFF) (Note 3) 25 Full OFF Output Leakage Current, ID(OFF) (Note 3) 25 Full ON Input Leakage Current, IS(ON) (Note 4) 25 Full 3 HI-390 Electrical Specifications Supplies = +15V, -15V; VIN = Logic Input. VIN for Logic "1" = 4V, for Logic "0" = 0.8V, Unless Otherwise Specified (Continued) TEST CONDITIONS TEMP (oC) MIN TYP MAX UNITS PARAMETER POWER SUPPLY CHARACTERISTICS Current, I+ (Note 8) 25 Full - 0.09 0.01 0.01 0.01 - 0.5 1 10 100 10 100 10 100 mA mA A A A A A A Current, I- (Note 8) 25 Full Current, I+ (Note 9) 25 Full Current, I- (Note 9) 25 Full NOTES: 3. VS = 14V, VD = 4. VS = VD = 14V. 5. The digital inputs are diode protected MOS gates and typical leakages of 1nA or less can be expected. 6. VS = 1VRMS , f = 500kHz, CL = 15pF, R L = 1K, C L = CFIXTURE + CPROBE, OFF Isolation = 20 Log VS /VD . 7. VS = 0V, CL = 10nF, Logic Drive = 5V pulse. Switches are symmetrical; S and D may be interchanged. Charge Injection = Q = CL x V. 8. VIN = 4V (one input, all other inputs = 0V). 9. VIN = 0.8V (all inputs). 14V. 2. VS = 10V, IOUT = 10mA. On resistance derived from the voltage measured across the switch under these conditions. Test Circuits and Waveforms 15V V+ RGEN = 0 S D RL 10k CL 10pF LOGIC INPUT (V) 6 4 2 0 LOGIC INPUT VGEN IN VLOGIC GND V0 0.4 0.8 TIME (s) 1.2 1.6 -15V FIGURE 1A. TEST CIRCUIT FIGURE 1B. LOGIC INPUT OUTPUT VOLTAGE (V) 10 5 0 VGEN = 10V (NOTE 10) OUTPUT VOLTAGE (V) 5 0 VGEN = 5V 0 0.4 0.8 TIME (s) 1.2 1.6 0 0.4 0.8 TIME (s) 1.2 1.6 FIGURE 1C. VANALOG = 10V FIGURE 1D. VANALOG = 5V 4 HI-390 Test Circuits and Waveforms (Continued) OUTPUT VOLTAGE (V) 5 0 -5 VGEN = 0V OUTPUT VOLTAGE (V) 0 -5 VGEN = -5V 0 0.4 0.8 TIME (s) 1.2 1.6 0 0.4 0.8 TIME (s) 1.2 1.6 FIGURE 1E. V ANALOG = 0V FIGURE 1F. VANALOG = -5V OUTPUT VOLTAGE (V) 0 -5 -10 VGEN = -10V 0 0.4 0.8 TIME (s) 1.2 1.6 FIGURE 1G. VANALOG = -10V NOTE: 10. If RGEN , RL or CL is increased, there will be proportional increases in rise and/or fall RC times. FIGURE 1. SWITCHING WAVEFORMS FOR VARIOUS ANALOG INPUT VOLTAGES Typical Performance Curves 80 V+ = +15V, V- = -15V 80 TA = 25 oC 60 125 oC 25 oC -55oC rDS(ON) () D 60 rDS(ON) () C 40 40 B A 20 0 -15 -10 -5 0 5 10 15 20 A B C D 0 -15 V+ = +15V, V- = -15V V+ = +10V, V- = -10V V+ = +7.5V, V- = -7.5V V+ = +5V, V- = -5V -10 -5 0 5 10 15 DRAIN VOLTAGE (V) DRAIN VOLTAGE (V) FIGURE 2. rDS(ON) vs VD FIGURE 3. rDS(ON) vs VD 5 HI-390 Typical Performance Curves 100 V+ = +15V, V- = -15V TA = 25oC, VS = 15V, R L = 2K POWER DISSIPATION (mW) 80 OFF ISOLATION (dB) 10 RL = 100 60 RL = 1k 40 (Continued) 100 V+ = +15V, V- = -15V CLOAD = 30pF, VS = 1VRMS 1.0 20 0.1 1 10 100 1K 10K 100K 1M 0 105 106 LOGIC SWITCHING FREQUENCY (50% DUTY CYCLE) (Hz) 107 108 FREQUENCY (Hz) FIGURE 4. DEVICE POWER DISSIPATION vs SWITCHING FREQUENCY (SINGLE LOGIC INPUT) 10.0 V+ = +15V, V- = -15V 10.0 FIGURE 5. OFF ISOLATION vs FREQUENCY V+ = +15V, V- = -15V | VD | = | VS | = 14V IS(OFF) OR ID(OFF) (nA) 1.0 ID(ON) (nA) 0.1 1.0 0.1 0.01 25 75 125 TEMPERATURE (oC) 0.01 25 75 125 TEMPERATURE (oC) FIGURE 6. IS(OFF) OR ID(OFF) vs TEMPERATURE (NOTE 11) NOTE: FIGURE 7. ID(ON) vs TEMPERATURE (NOTE 11) 11. The net leakage into the source or drain is the N-Channel leakage minus the P-Channel leakage. This difference can be positive, negative or zero depending on the analog voltage and temperature, and will vary greatly from unit to unit. 60 16 50 CD(ON) (pF) 12 40 CIN (pF) 8 TRANSITION (INDETERMINATE DUE TO ACTIVE INPUT) 30 4 20 0 2 4 6 8 10 12 14 16 0 2 4 6 8 10 12 14 16 DRAIN VOLTAGE (V) INPUT VOLTAGE (V) FIGURE 8. OUTPUT ON CAPACITANCE vs DRAIN VOLTAGE FIGURE 9. DIGITAL INPUT CAPACITANCE vs INPUT VOLTAGE 6 HI-390 Typical Performance Curves 300 V+ = +15V, V- = -15V VINH = 4.0V, VINL = 0V tON tON , tOFF (ns) tON , tOFF (ns) 200 300 tON V+ = +15V, TA = 25oC VINH = 4V, VINL = 0V (Continued) 200 tOFF tOFF 100 100 0 -55 -35 -15 5 25 45 65 TEMPERATURE (oC) 85 105 125 0 5 10 NEGATIVE SUPPLY (V) 15 FIGURE 10. SWITCHING TIME vs TEMPERATURE FIGURE 11. SWITCHING TIME vs NEGATIVE SUPPLY VOLTAGE 1.8 INPUT SWITCHING THRESHOLD (V) 1.6 1.4 tON, tOFF (s) 1.2 1.0 0.8 0.6 tON 0.4 tOFF 0.2 0 0 5 10 15 POSITIVE SUPPLY VOLTAGE (V) V- = -15V, TA = 25 oC VINH = 4.0V, VINL = 0V 7 V- = -15V, TA = 25 oC 6 5 4 3 2 1 0 0 5 10 15 POSITIVE SUPPLY VOLTAGE (V) FIGURE 12. SWITCHING TIME vs POSITIVE SUPPLY VOLTAGE FIGURE 13. INPUT SWITCHING THRESHOLD vs POSITIVE SUPPLY VOLTAGE 7 HI-390 FN Ceramic Dual-In-Line Frit Seal Packages (CERDIP) c1 -A-DBASE METAL E b1 M -Bbbb S BASE PLANE SEATING PLANE S1 b2 b ccc M C A - B S AA C A-B S D Q -CA L DS M (b) SECTION A-A (c) LEAD FINISH F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A) 16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE INCHES SYMBOL A b b1 b2 b3 c MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.220 MAX 0.200 0.026 0.023 0.065 0.045 0.018 0.015 0.840 0.310 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 5.59 MAX 5.08 0.66 0.58 1.65 1.14 0.46 0.38 21.34 7.87 NOTES 2 3 4 2 3 5 5 6 7 2, 3 8 Rev. 0 4/94 eA c1 D E e eA eA/2 L Q S1 e DS eA/2 c 0.100 BSC 0.300 BSC 0.150 BSC 0.125 0.015 0.005 90o 16 0.200 0.060 105o 0.015 0.030 0.010 0.0015 2.54 BSC 7.62 BSC 3.81 BSC 3.18 0.38 0.13 90o 16 5.08 1.52 105o 0.38 0.76 0.25 0.038 aaa M C A - B S D S NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. aaa bbb ccc M N All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 8 |
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